1. Technical Field
Embodiments of the present disclosure generally relate to a semiconductor system, and more particularly, to program and read operations.
2. Related Art
Electrically erasable programmable read only memory (EEPROM) devices are nonvolatile memory devices whose data can be erased using an electric bias instead of an ultraviolet (UV) light source. Each of the EEPROM devices may include a plurality of memory cells, and each of the memory cells may include a floating gate that is electrically insulated. A logic level of the data stored in the memory cell can be discriminated according to whether the floating gate contains electric charges or not. In general, a memory cell including the floating gate (hereinafter, referred to as a floating gate memory cell) is formed in and on an integrated circuit (IC) substrate such as a semiconductor substrate. For example, the floating gate memory cell is formed to include source and drain regions spaced apart from each other as well as the floating gate disposed on a channel region between the source and drain regions. The floating gate may be formed of a doped polysilicon layer and may be electrically insulated from other cell components by a dielectric material such as an oxide layer. A gate oxide layer may be disposed between the channel region and the floating gate. Further, a control gate may be disposed on a top surface of the floating gate opposite to the channel region and may be formed of a doped polysilicon layer. The control gate may be electrically insulated from the floating gate by another dielectric layer so called ‘an inter-gate dielectric layer’. As a result, the floating gate may be electrically insulated from the channel region and the control gate. Electric charges are injected into or removed from the floating gate during a program operation or an erasure operation. Other nonvolatile memory devices may include polymer memory devices, ferroelectric RAM (FeRAM) devices, Ovonics unified memory (OUM) device (also, known as ‘phase change random access memory (PCRAM) devices’) and magnetic RAM (MRAM) devices.
The nonvolatile memory devices may further include flash memory devices. In general, each of the flash memory devices may include a memory array having a plurality of flash memory cells. Each of the flash memory cells may include a floating gate or a charge trapping layer which is buried in a field effect transistor (FET). The flash memory cells may be grouped into a plurality of sections which are also referred to as ‘erasure blocks’. The floating gate memory cells may be individually programmed by injecting electric charges (e.g., negative charges) into the corresponding floating gate using a tunneling effect. All the floating gate memory cells in each erasure block may be simultaneously erased by removing the negative charges stored in the floating gates thereof during a block erasure operation. In recent flash memory devices employing the non-conductive charge strapping layers, a single memory cell can be programmed to have multi-bit data by injecting electric charges into portions of the non-conductive charge trapping layers adjacent to the source regions and/or the drain regions. Further, in recent flash memory devices employing the floating gates, a single memory cell can be programmed to have multi-bit data by determining a plurality of critical charge levels of each memory cell.
In general, a single row (e.g., a single page) of memory cells of the flash memory devices may be programmed by applying a program voltage signal or a series of program pulse signals to a control gate.